8 search results - page 2 / 2 » Scaling to the End of Silicon with EDGE Architectures |
CCR
2004
13 years 5 months ago
2004
As the Internet grows in size, it becomes crucial to understand how the speeds of links in the network must improve in order to sustain the pressure of new end-nodes being added e...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...