19 search results - page 1 / 4 » Scheduling Coarse-Grain Operations for VLIW Processors |
ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
HPCA
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...