19 search results - page 3 / 4 » Scheduling Coarse-Grain Operations for VLIW Processors |
SAC
2004
ACM
13 years 11 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
CGO
2004
IEEE
13 years 9 months ago
2004
IEEE
Predicated execution enables the removal of branches by converting segments of branching code into sequences of conditional operations. An important side effect of this transforma...
TCAD
2002
13 years 5 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
LCTRTS
2001
Springer
13 years 10 months ago
2001
Springer
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
SIGOPSE
1998
ACM
13 years 10 months ago
1998
ACM
MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynam...