—In this paper, we address the scheduling problem for Clos-network switches with no buffers at the central stage. Existing scheduling (dispatching) algorithms for this type of sw...
Mei Yang, Mayauna McCullough, Yingtao Jiang, Jun Z...
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wlad...
With the rapid development of broadband applications, the capability of networks to provide quality of service (QoS) has become an important issue. Fair scheduling algorithms are ...
— Dealing with RTTs (Round Trip Time) in IQ switches has been recently recognized as a challenging problem, especially if considering distributed (multi-chip) scheduler implement...
Alessandra Scicchitano, Andrea Bianco, Paolo Giacc...
— In this paper, we propose a fair and simple high-performance scheduling algorithm for Combined Input-Crosspoint-Queued Switches, which is called Tracking Fair Quota Allocation ...
Nan Hua, Peng Wang, Depeng Jin, Lieguang Zeng, Bin...