Sciweavers

23 search results - page 4 / 5
» Scheduling Processing Resources in Programmable Routers
Sort
View
PPOPP
2010
ACM
13 years 11 months ago
Thread to strand binding of parallel network applications in massive multi-threaded systems
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
13 years 9 months ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...
DATE
2002
IEEE
86views Hardware» more  DATE 2002»
13 years 10 months ago
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems
By using a macro/micro state model we show how assumptions on the resolution of logical and physical timing of computation in computer systems has resulted in design methodologies...
JoAnn M. Paul, Donald E. Thomas
IJNSEC
2007
137views more  IJNSEC 2007»
13 years 5 months ago
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
Arshad Aziz, Nassar Ikram
HICSS
2009
IEEE
106views Biometrics» more  HICSS 2009»
14 years 4 hour ago
A Radical Approach to Network-on-Chip Operating Systems
Operating systems were created to provide multiple tasks with access to scarce hardware resources like CPU, memory, or storage. Modern programmable hardware, however, may contain ...
Michael Engel, Olaf Spinczyk