221 search results - page 1 / 45 » Scheduling instruction effects for a statically pipelined pr... |
RTSS
2008
IEEE
13 years 11 months ago
2008
IEEE
Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case exe...
HPCA
1995
IEEE
13 years 8 months ago
1995
IEEE
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
RTS
2006
13 years 4 months ago
2006
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...