Sciweavers

Share
RTS
2006

Modeling out-of-order processors for WCET analysis

8 years 6 months ago
Modeling out-of-order processors for WCET analysis
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typically model the timing effects of micro-architectural features in modern processors (such as pipeline, cache, branch prediction) to obtain safe and tight estimates. In this paper, we model out-of-order superscalar processor pipelines for WCET analysis. The analysis is, in general, difficult even for a basic block (a sequence of instructions with single-entry and single-exit points) if some of the instructions have variable latencies. This is because the WCET of a basic block on out-of-order pipelines cannot be obtained by assuming maximum latencies of the individual instructions. Our timing estimation technique for a basic block proceeds by a fixed-point analysis of the time intervals at which the instructions enter/leave a pipeline stage. To extend our estimation to whole programs, we use Integer Linear Progr...
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2006
Where RTS
Authors Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
Comments (0)
books