133 search results - page 27 / 27 » Seamless integration of layout and simulation |
DAC
2008
ACM
14 years 6 months ago
2008
ACM
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
DATE
2009
IEEE
14 years 1 days ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...