Sciweavers

72 search results - page 4 / 15
» Secure function evaluation with ordered binary decision diag...
Sort
View
ISMVL
2000
IEEE
98views Hardware» more  ISMVL 2000»
13 years 10 months ago
Implementation of Multiple-Output Functions Using PQMDDs
A sequential realization of multiple-output logic functions is presented. A conventional sequential realization is based on SBDDs (Shared reduced ordered Binary Decision Diagrams)...
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
EOR
2011
140views more  EOR 2011»
13 years 22 days ago
Power indices of simple games and vector-weighted majority games by means of binary decision diagrams
A simple game is a pair consisting of a finite set N of players and a set W ⊆ 2N of winning coalitions. (Vector-)weighted majority games ((V)WMG) are a special case of simple ga...
Stefan Bolus
MICRO
2000
IEEE
162views Hardware» more  MICRO 2000»
13 years 9 months ago
Accurate and efficient predicate analysis with binary decision diagrams
Functionality and performance of EPIC architectural features depend on extensive compiler support. Predication, one of these features, promises to reduce control flow overhead and...
John W. Sias, Wen-mei W. Hwu, David I. August
ICCD
2006
IEEE
125views Hardware» more  ICCD 2006»
14 years 2 months ago
Partial Functional Manipulation Based Wirelength Minimization
—In-place flipping of rectangular blocks/cells can potentially reduce the wirelength of a floorplan/placement solution without changing the chip area, In a recent work [Hao 05], ...
Avijit Dutta, David Z. Pan
GLVLSI
1996
IEEE
145views VLSI» more  GLVLSI 1996»
13 years 10 months ago
Boolean Function Representation Using Parallel-Access Diagrams
Inthispaperweintroduceanondeterministiccounterpart to Reduced, Ordered Binary Decision Diagrams for the representation and manipulation of logic functions. ROBDDs are conceptually...
Valeria Bertacco, Maurizio Damiani