4 search results - page 1 / 1 » Secure scan: a design-for-test architecture for crypto chips |
DAC
2005
ACM
14 years 5 months ago
2005
ACM
TODAES
2011
12 years 11 months ago
2011
—In this paper, we present an attack on stream cipher implementations by determining the scan chain structure of the linear feedback shift registers in their implementations. Alt...
ACSAC
2000
IEEE
13 years 9 months ago
2000
IEEE
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
ACSAC
2008
IEEE
13 years 11 months ago
2008
IEEE
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...