Sciweavers

46 search results - page 8 / 10
» Self Testing SoC with Reduced Memory Requirements and Minimi...
Sort
View
EGH
2009
Springer
13 years 3 months ago
Efficient stream compaction on wide SIMD many-core architectures
Stream compaction is a common parallel primitive used to remove unwanted elements in sparse data. This allows highly parallel algorithms to maintain performance over several proce...
Markus Billeter, Ola Olsson, Ulf Assarsson
ICS
1999
Tsinghua U.
13 years 9 months ago
Fast cluster failover using virtual memory-mapped communication
This paper proposes a novel way to use virtual memorymapped communication (VMMC) to reduce the failover time on clusters. With the VMMC model, applications’ virtual address spac...
Yuanyuan Zhou, Peter M. Chen, Kai Li
GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
13 years 12 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra
PLDI
2004
ACM
13 years 10 months ago
Vectorization for SIMD architectures with alignment constraints
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
EUROGRAPHICS
2010
Eurographics
14 years 2 months ago
HCCMeshes: Hierarchical-Culling oriented Compact Meshes
Hierarchical culling is a key acceleration technique used to efficiently handle massive models for ray tracing, collision detection, etc. To support such hierarchical culling, bo...
Tae-Joon Kim, Yongyoung Byun, Yongjin Kim, Bochang...