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GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
13 years 10 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
LCTRTS
2010
Springer
13 years 10 months ago
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, cac...
Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
13 years 9 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
ESWA
2008
151views more  ESWA 2008»
13 years 5 months ago
Automated diagnosis of sewer pipe defects based on machine learning approaches
In sewage rehabilitation planning, closed circuit television (CCTV) systems are the widely used inspection tools in assessing sewage structural conditions for non man entry pipes....
Ming-Der Yang, Tung-Ching Su
SAC
2008
ACM
13 years 4 months ago
A hybrid software-based self-testing methodology for embedded processor
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee