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SIGSOFT
2003
ACM
14 years 5 months ago
Behaviour model elaboration using partial labelled transition systems
State machine based formalisms such as labelled transition systems (LTS) are generally assumed to be complete descriptions m behaviour at some level of abstraction: if a labelled ...
Sebastián Uchitel, Jeff Kramer, Jeff Magee
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 5 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
FORMATS
2006
Springer
13 years 8 months ago
Integrating Discrete- and Continuous-Time Metric Temporal Logics Through Sampling
Abstract. Real-time systems usually encompass parts that are best described by a continuous-time model, such as physical processes under control, together with other components tha...
Carlo A. Furia, Matteo Rossi