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ICSEA
2007
IEEE
13 years 11 months ago
Test Data Generation from UML State Machine Diagrams using GAs
Automatic test data generation helps testers to validate software against user requirements more easily. Test data can be generated from many sources; for example, experience of t...
Chartchai Doungsa-ard, Keshav P. Dahal, M. Alamgir...
VTS
2000
IEEE
113views Hardware» more  VTS 2000»
13 years 9 months ago
Hidden Markov and Independence Models with Patterns for Sequential BIST
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
Laurent Bréhélin, Olivier Gascuel, G...
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 1 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
ICSE
2008
IEEE-ACM
14 years 5 months ago
Using JULE to generate a compliance test suite for the UML standard
The Java-UML Lightweight Enumerator (JULE) tool implements a vitally important aspect of the framework for software tool certification - test suite generation. The framework uses ...
Panuchart Bunyakiati, Anthony Finkelstein, James S...
TABLEAUX
1998
Springer
13 years 9 months ago
Model Checking: Historical Perspective and Example (Extended Abstract)
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
Edmund M. Clarke, Sergey Berezin