VTS 2000 - PDF Preprint Papers

VTS 2000 IEEE VLSI Test Symposium

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed VTS-2000 Paper

click to vote

VTS
2000
IEEE

167views Hardware» more VTS 2000»

Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis

13 years 9 months ago

Download cadlab.ece.ucsb.edu

The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...

Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	167	Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis	claim
2	137	Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method	claim
3	126	Static Compaction Techniques to Control Scan Vector Power Dissipation	claim
4	114	Detection of CMOS Defects under Variable Processing Conditions	claim
5	113	Hidden Markov and Independence Models with Patterns for Sequential BIST	claim
6	108	High-Level Observability for Effective High-Level ATPG	claim
7	108	Cold Delay Defect Screening	claim
8	103	Invariance-Based On-Line Test for RTL Controller-Datapath Circuits	claim
9	100	Functional Memory Faults: A Formal Notation and a Taxonomy	claim
10	99	Virtual Scan Chains: A Means for Reducing Scan Length in Cores	claim
11	97	A Low-Speed BIST Framework for High-Performance Circuit Testing	claim
12	95	DEFUSE: A Deterministic Functional Self-Test Methodology for Processors	claim
13	95	Word Voter: A New Voter Design for Triple Modular Redundant Systems	claim
14	94	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set	claim
15	89	Fault Escapes in Duplex Systems	claim
16	84	ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits	claim
17	83	Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling	claim
18	76	Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems	claim
19	70	Thermal Testing: Fault Location Strategies	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers