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» Serial-link bus: a low-power on-chip bus architecture
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DAC
2009
ACM
14 years 7 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
VLSID
2002
IEEE
87views VLSI» more  VLSID 2002»
14 years 6 months ago
Weight-Based Bus-Invert Coding for Low-Power Applications
Rung-Bin Lin, Chi-Ming Tsai
DAC
2001
ACM
14 years 7 months ago
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
Haris Lekatsas, Jörg Henkel
VLSID
2003
IEEE
108views VLSI» more  VLSID 2003»
14 years 6 months ago
A Low Power-Delay Product Page-Based Address Bus Coding Method
The working-zone encoding (WZE) method employing locality of memory reference was previously proposed to reduce address bus switching activity. This paper presents an encoding met...
Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 10 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner