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ASPDAC
2005
ACM
79views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-...
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
13 years 7 months ago
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho S...