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APCSAC
2001
IEEE
13 years 8 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
SC
2009
ACM
13 years 12 months ago
Enabling high-fidelity neutron transport simulations on petascale architectures
The UNIC code is being developed as part of the DOE’s Nuclear Energy Advanced Modeling and Simulation (NEAMS) program. UNIC is an unstructured, deterministic neutron transport c...
Dinesh K. Kaushik, Micheal Smith, Allan Wollaber, ...
LCTRTS
2007
Springer
13 years 11 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
13 years 12 months ago
Light NUCA: A proposal for bridging the inter-cache latency gap
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
Darío Suárez Gracia, Teresa Monreal,...
IISWC
2009
IEEE
13 years 11 months ago
SD-VBS: The San Diego Vision Benchmark Suite
—In the era of multi-core, computer vision has emerged as an exciting application area which promises to continue to drive the demand for both more powerful and more energy effi...
Sravanthi Kota Venkata, Ikkjin Ahn, Donghwan Jeon,...