Sciweavers

67 search results - page 2 / 14
» Simultaneously improving code size, performance, and energy ...
Sort
View
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
13 years 10 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
CODES
2002
IEEE
13 years 9 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
LCTRTS
2010
Springer
13 years 6 months ago
An efficient code update scheme for DSP applications in mobile embedded systems
DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advanta...
Weijia Li, Youtao Zhang
HIPEAC
2007
Springer
13 years 10 months ago
Performance/Energy Optimization of DSP Transforms on the XScale Processor
The XScale processor family provides user-controllable independent configuration of CPU, bus, and memory frequencies. This feature introduces another handle for the code optimizat...
Paolo D'Alberto, Markus Püschel, Franz Franch...
CODES
2006
IEEE
13 years 10 months ago
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffe...
Roshan G. Ragel, Sri Parameswaran