Sciweavers

32 search results - page 2 / 7
» Sizing of Clock Distribution Networks for High Performance C...
Sort
View
CNSR
2010
IEEE
164views Communications» more  CNSR 2010»
13 years 8 months ago
Buffered Crossbar Fabrics Based on Networks on Chip
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin
IPPS
2002
IEEE
13 years 9 months ago
Can User-Level Protocols Take Advantage of Multi-CPU NICs?
Modern high speed interconnects such as Myrinet and Gigabit Ethernet have shifted the bottleneck in communication from the interconnect to the messaging software at the sending an...
Piyush Shivam, Pete Wyckoff, Dhabaleswar K. Panda
HOTI
2005
IEEE
13 years 10 months ago
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
A partitioned TCAM-based search engine is presented that increases packet forwarding rate multiple times over traditional TCAMs. The model works for IPv4 and IPv6 packet forwardin...
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Pa...
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
13 years 10 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
HPCA
2006
IEEE
14 years 5 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal