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» Sizing of Processing Arrays for FPGA-Based Computation
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IPPS
2006
IEEE
13 years 11 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
ICIP
1999
IEEE
14 years 7 months ago
Quadtrees for Embedded Surface Visualization: Constraints and Efficient Data Structures
The quadtree data structure is widely used in digital image processing and computer graphics for modeling spatial segmentation of images and surfaces. A quadtree is a tree in whic...
Laurent Balmelli, Jelena Kovacevic, Martin Vetterl...
EDBT
2010
ACM
133views Database» more  EDBT 2010»
14 years 14 days ago
FPGAs: a new point in the database design space
In line with the insight that “one size” of databases will not fit all application needs [19], the database community is currently exploring various alternatives to commodity...
René Müller, Jens Teubner
LREC
2008
130views Education» more  LREC 2008»
13 years 7 months ago
Detecting Co-Derivative Documents in Large Text Collections
We have analyzed the SPEX algorithm by Bernstein and Zobel (2004) for detecting co-derivative documents using duplicate n-grams. Although we totally agree with the claim that not ...
Jan Pomikálek, Pavel Rychlý
CHI
2004
ACM
14 years 6 months ago
Z-Tiles: building blocks for modular, pressure-sensing floorspaces
A new interactive floorspace has been developed which uses modular nodes connected together to create a pressuresensitive area of varying size and shape, giving it the potential t...
Bruce Richardson, Joseph A. Paradiso, Krispin Leyd...