Sciweavers

49 search results - page 9 / 10
» Sizing of Processing Arrays for FPGA-Based Computation
Sort
View
CCGRID
2010
IEEE
13 years 6 months ago
Selective Recovery from Failures in a Task Parallel Programming Model
Abstract--We present a fault tolerant task pool execution environment that is capable of performing fine-grain selective restart using a lightweight, distributed task completion tr...
James Dinan, Arjun Singri, P. Sadayappan, Sriram K...
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
13 years 11 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
ICDCS
2012
IEEE
11 years 7 months ago
Scalable Name Lookup in NDN Using Effective Name Component Encoding
—Name-based route lookup is a key function for Named Data Networking (NDN). The NDN names are hierarchical and have variable and unbounded lengths, which are much longer than IPv...
Yi Wang, Keqiang He, Huichen Dai, Wei Meng, Junche...
IPPS
1999
IEEE
13 years 9 months ago
Design and Implementation of a Scalable Parallel System for Multidimensional Analysis and OLAP
Multidimensional Analysis and On-Line Analytical Processing (OLAP) uses summary information that requires aggregate operations along one or more dimensions of numerical data value...
Sanjay Goil, Alok N. Choudhary
ICDCS
2009
IEEE
14 years 2 months ago
Pushing the Envelope: Extreme Network Coding on the GPU
While it is well known that network coding achieves optimal flow rates in multicast sessions, its potential for practical use has remained to be a question, due to its high compu...
Hassan Shojania, Baochun Li