10 search results - page 2 / 2 » Skew scheduling and clock routing for improved tolerance to ... |
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
ISCA
2007
IEEE
13 years 11 months ago
2007
IEEE
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...