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CODES
2005
IEEE
13 years 11 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
CODES
1996
IEEE
13 years 10 months ago
A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study
This reported work applies a transformational synthesis approach to hardware/software codesign. In this approach, the process of algorithm design is coupled early on with hardware...
Tommy King-Yin Cheung, Graham R. Hellestrand, Pras...
ECMDAFA
2010
Springer
151views Hardware» more  ECMDAFA 2010»
13 years 9 months ago
Generative Technologies for Model Animation in the TopCased Platform
Domain Specific Modeling Languages (DSML) are more and more used to handle high level concepts, and thus bring complex software development under control. The increasingly recurrin...
Xavier Crégut, Benoît Combemale, Marc...
PLDI
2010
ACM
13 years 9 months ago
Parameterized Verification of Transactional Memories
We describe an automatic verification method to check whether transactional memories ensure strict serializability--a key property assumed of the transactional interface. Our main...
Michael Emmi, Rupak Majumdar, Roman Manevich
IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
14 years 5 days ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand