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DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 5 hour ago
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
Drew C. Ness, David J. Lilja
MICRO
2006
IEEE
159views Hardware» more  MICRO 2006»
13 years 5 months ago
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...