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DATE
2008
IEEE

Guiding Circuit Level Fault-Tolerance Design with Statistical Methods

10 years 6 months ago
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redundancy approaches. We present the results from a screening experiment to identify significant parameters in circuit level soft error simulations to guide such approaches to faulttolerance. This approach allows us to assess which parameters will have the most significance for reducing soft error rates and the impact that process variation will have on the accuracy of soft error rate estimates. We identify supply voltage and transistor type as being the most significant parameters affecting soft errors in logic cells across several technology scales. Additionally, we provide a ranking of more than a dozen parameters, across four technology scales, based on the significance of their impact on soft error rates.
Drew C. Ness, David J. Lilja
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DATE
Authors Drew C. Ness, David J. Lilja
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