In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
In thispaper,a mathematicalmethodfor analysis of synchronous packet-switching interconnection networks with jinite buffering capacity at the output of switching elements ispresent...
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...
This work presents an approach for realizing Model-Driven software engineering in the distributed and multi-developers context. It particularly focuses on the scalability problems...