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JSS
2006
104views more  JSS 2006»
13 years 5 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
EUROMICRO
1996
IEEE
13 years 9 months ago
Performance Analysis of Packet Switching Interconnection Networks with Finite Buffers
In thispaper,a mathematicalmethodfor analysis of synchronous packet-switching interconnection networks with jinite buffering capacity at the output of switching elements ispresent...
Aristotel Tentov, Aksenti L. Grnarov
MEMOCODE
2003
IEEE
13 years 10 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
IPPS
2003
IEEE
13 years 10 months ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...
SAC
2008
ACM
13 years 4 months ago
Collaborative software engineering on large-scale models: requirements and experience in ModelBus
This work presents an approach for realizing Model-Driven software engineering in the distributed and multi-developers context. It particularly focuses on the scalability problems...
Prawee Sriplakich, Xavier Blanc, Marie-Pierre Gerv...