67 search results - page 2 / 14 » Software-based instruction caching for embedded processors |
SAMOS
2005
Springer
13 years 10 months ago
2005
Springer
In this paper, we introduce the concept of flux caches envisioned to improve processor performance by dynamically changing the cache organization and implementation. Contrary to t...
ATS
2003
IEEE
13 years 10 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
RTSS
2008
IEEE
13 years 11 months ago
2008
IEEE
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...