Sciweavers

25 search results - page 5 / 5
» Sparse Decoding of Low Density Parity Check Codes Using Marg...
Sort
View
CORR
2006
Springer
105views Education» more  CORR 2006»
13 years 5 months ago
A Combinatorial Family of Near Regular LDPC Codes
Abstract-- An elementary combinatorial Tanner graph construction for a family of near-regular low density parity check (LDPC) codes achieving high girth is presented. These codes a...
K. Murali Krishnan, Rajdeep Singh, L. Sunil Chandr...
DFT
2007
IEEE
135views VLSI» more  DFT 2007»
13 years 11 months ago
Fault Secure Encoder and Decoder for Memory Applications
We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry....
Helia Naeimi, André DeHon
CORR
2010
Springer
261views Education» more  CORR 2010»
13 years 2 months ago
Analysis of Quasi-Cyclic LDPC codes under ML decoding over the erasure channel
In this paper, we show that over the binary erasure channel, Quasi-Cyclic LDPC codes can efficiently accommodate the hybrid iterative/ML decoding. We demonstrate that the quasicycl...
Mathieu Cunche, Valentin Savin, Vincent Roca
VTC
2008
IEEE
13 years 11 months ago
Construction of Regular Quasi-Cyclic Protograph LDPC codes based on Vandermonde Matrices
Abstract— In this contribution, we investigate the attainable performance of quasi-cyclic (QC) protograph Low-Density Parity-Check (LDPC) codes for transmission over both Additiv...
Nicholas Bonello, Sheng Chen, Lajos Hanzo
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
13 years 10 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...