17 search results - page 2 / 4 » Specification and Checking of Software Contracts for Conditi... |
KBSE
2007
IEEE
13 years 11 months ago
2007
IEEE
Threat modeling analyzes how an adversary might attack a system by supplying it with malicious data or interacting with it. The analysis uses a Data Flow Diagram (DFD) to describe...
SAC
2010
ACM
13 years 2 months ago
2010
ACM
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
ATAL
2008
Springer
13 years 6 months ago
2008
Springer
We explore the problem of specification and verification of compliance in agent based Web service compositions. We use the formalism of temporal-epistemic logic suitably extended ...
ICESS
2005
Springer
13 years 10 months ago
2005
Springer
PeaCE(Ptolemy extension as a Codesign Environment) was developed for the hardware and software codesign framework which allows us to express both data flow and control flow. The fF...
CASES
2008
ACM
13 years 6 months ago
2008
ACM
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...