2 search results - page 1 / 1 » Spectral shaping of timing mismatches in time-interleaved an... |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Mismatches between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) cause undesirable distortions in the output spectrum. To reduce t...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— We introduce spectral shaping of timing mismatches in time-interleaved analog-to-digital converters (TIADCs). We show how to reorder the channel ADC sequence in order to achiev...