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CF
2005
ACM
13 years 6 months ago
Reducing misspeculation overhead for module-level speculative execution
Thread-level speculative execution is a technique that makes it possible for a wider range of single-threaded applications to make use of the processing resources in a chip multip...
Fredrik Warg, Per Stenström
ISPAN
2000
IEEE
13 years 9 months ago
Comprehensive Evaluation of an Instruction Reissue Mechanism
In this paper, we evaluate a mechanism to reissue instructions on the mispredicted speculation path. An instruction which is once dispatched to a functional unit during mispredict...
Toshinori Sato, Itsujiro Arita
HPCA
2003
IEEE
14 years 5 months ago
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
María Jesús Garzarán, Milos P...
IPPS
2007
IEEE
13 years 11 months ago
Microarchitectural Support for Speculative Register Renaming
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission ...
Jesús Alastruey, Teresa Monreal, Víc...
MICRO
1999
IEEE
131views Hardware» more  MICRO 1999»
13 years 9 months ago
Value Prediction for Speculative Multithreaded Architectures
The speculative multithreading paradigm (speculative threadlevel parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitect...
Pedro Marcuello, Jordi Tubella, Antonio Gonz&aacut...