2 search results - page 1 / 1 » Speeding Up The Byzantine Fault Diagnosis Using Symbolic Sim... |
VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
ATS
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper addresses the problem of locating the stuckopen faults in a manufactured IC with scan flip-flops. Unlike most previous methods that only aim at identifying the faulty s...