14 search results - page 1 / 3 » Speedup of Self-Timed Digital Systems Using Early Completion |
ISVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
An Early Completion technique is developed to significantly increase the throughput of NULL Convention self-timed digital systems without impacting latency or compromising their s...
JSA
2006
13 years 4 months ago
2006
A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, c...
DATE
2010
IEEE
13 years 2 months ago
2010
IEEE
The H.264/AVC video encoder standard significantly improves the compression efficiency by using variable block-sized Inter (P) and Intra (I) Macroblock (MB) coding modes. In this p...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
RSP
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...