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» Sphere Decoding for Multiprocessor Architectures
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ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
13 years 9 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
SLIP
2009
ACM
14 years 14 hour ago
Honeycomb-structured computational interconnects and their scalable extension to spherical domains
The present paper is part of a larger effort to redesign, from the ground up, the best possible interconnect topologies for switchless multiprocessor computer systems. We focus he...
Joseph B. Cessna, Thomas R. Bewley
TSP
2008
101views more  TSP 2008»
13 years 5 months ago
Reduced-Complexity Soft MIMO Detection Based on Causal and Noncausal Decision Feedback
We present a reduced-complexity soft detection (RCSD) scheme geared to multiple-input multiple-output (MIMO) systems with spatial domain multiplexing leading to layered space-time ...
Yong Li, Jaekyun Moon