4 search results - page 1 / 1 » Staged Reads: Mitigating the impact of DRAM writes on DRAM r... |
HPCA
2012
IEEE
12 years 13 days ago
2012
IEEE
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
As DRAM and other charge memories reach scaling limits, resistive memories, such as phase change memory (PCM), may permit continued scaling of main memories. However, while PCM ma...
ASPLOS
2010
ACM
13 years 8 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
CIDR
2011
12 years 8 months ago
2011
Phase change memory (PCM) is an emerging memory technology with many attractive features: it is non-volatile, byte-addressable, 2–4X denser than DRAM, and orders of magnitude be...