150 search results - page 29 / 30 » Staged memory scheduling: Achieving high performance and sca... |
OOPSLA
2009
Springer
14 years 9 hour ago
2009
Springer
The shift from single to multiple core architectures means that programmers must write concurrent, multithreaded programs in order to increase application performance. Unfortunate...
PPOPP
2011
ACM
12 years 8 months ago
2011
ACM
In recent years, GPUs have emerged as an extremely cost-effective means for achieving high performance. Many application developers, including those with no prior parallel program...
IEEEPACT
2005
IEEE
13 years 11 months ago
2005
IEEE
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
IJPP
2006
13 years 5 months ago
2006
Abstract. In order to address the problems faced in the wireless communications domain, picoChip has devised the picoArrayTM . The picoArrayTM is a tiled-processor architecture, co...
TPDS
2010
13 years 4 days ago
2010
As an efficient distribution mechanism, Peer-to-Peer (P2P) technology has become a tremendously attractive solution to offload servers in large-scale video streaming applications. ...