3 search results - page 1 / 1 » Static Consistency Checking for Verilog Wire Interconnects |
PEPM
2009
ACM
15 years 5 months ago
2009
ACM
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
FCCM
1997
IEEE
13 years 9 months ago
1997
IEEE
The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut o...