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RTAS
2005
IEEE
13 years 10 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
ISCA
2007
IEEE
167views Hardware» more  ISCA 2007»
13 years 11 months ago
New cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
Zhenghong Wang, Ruby B. Lee
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
13 years 11 months ago
Finding concurrency bugs with context-aware communication graphs
Incorrect thread synchronization often leads to concurrency bugs that manifest nondeterministically and are difficult to detect and fix. Past work on detecting concurrency bugs ...
Brandon Lucia, Luis Ceze
SERA
2004
Springer
13 years 10 months ago
NuEditor - A Tool Suite for Specification and Verification of NuSCR
NuEditor is a tool suite supporting specification and verification of software requirements written in NuSCR. NuSCR extends SCR (Software Cost Reduction) notation that has been us...
Jaemyung Cho, Junbeom Yoo, Sung Deok Cha
CN
2002
77views more  CN 2002»
13 years 4 months ago
Architecture of a Web server accelerator
We describe the design, implementation and performance of a high-performance Web server accelerator which runs on an embedded operating system and improves Web server performance ...
Junehwa Song, Arun Iyengar, Eric Levy-Abegnoli, Da...