328 search results - page 66 / 66 » Static performance prediction of skeletal parallel programs |
ICS
2003
Tsinghua U.
13 years 10 months ago
2003
Tsinghua U.
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
HPCA
2008
IEEE
14 years 5 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
ICPP
2002
IEEE
13 years 9 months ago
2002
IEEE
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...