Sciweavers

48 search results - page 9 / 10
» Static statistical timing analysis for latch-based pipeline ...
Sort
View
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
14 years 2 months ago
Guaranteeing performance yield in high-level synthesis
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current hi...
Wei-Lun Hung, Xiaoxia Wu, Yuan Xie
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
13 years 12 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
14 years 2 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
DATE
2010
IEEE
178views Hardware» more  DATE 2010»
13 years 10 months ago
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
GLVLSI
2006
IEEE
144views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Crosstalk analysis in nanometer technologies
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
Shahin Nazarian, Ali Iranli, Massoud Pedram