306 search results - page 3 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
The intellectual property (IP) business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propo...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
CSREAESA
2006
13 years 6 months ago
2006
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
