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CSREAESA
2006

Delay-Reduced Combinational Logic Synthesis using Multiplexers

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Delay-Reduced Combinational Logic Synthesis using Multiplexers
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is used as the only design unit for defining any logic function specified by minterms. An algorithm is proposed that does exhaustive branching to reduce the number of levels and/or modules required to implement any logic function. The algorithm identifies a single variable or a function at the control input of the multiplexer which leads to an implementation with reduced number of levels and/or hardware. Simulation is done upto 9 variable functions using two levels. The approach attains a reduction in delay and/or power over other implementations of functions having larger number of variables. Theoretically, the algorithm can handle completely specified functions of any number of variables.
Rekha K. James, T. K. Shahana, K. Poulose Jacob, S
Added 30 Oct 2010
Updated 30 Oct 2010
Type Conference
Year 2006
Where CSREAESA
Authors Rekha K. James, T. K. Shahana, K. Poulose Jacob, Sreela Sasi
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