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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 1 months ago
Statistical based link insertion for robust clock network design
We present a statistical based non-tree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the...
Wai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venk...
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
13 years 11 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh ...
DAC
2004
ACM
14 years 5 months ago
Reducing clock skew variability via cross links
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
ISPD
2006
ACM
108views Hardware» more  ISPD 2006»
13 years 10 months ago
Statistical clock tree routing for robustness to process variations
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu