11 search results - page 1 / 3 » Stochastic Modeling and Performance Evaluation for Digital C... |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
WCE
2007
13 years 5 months ago
2007
—Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-n...
ENTCS
2008
13 years 4 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...