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» Storage coding for wear leveling in flash memories
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SIGOPS
2010
83views more  SIGOPS 2010»
13 years 3 months ago
Empirical evaluation of NAND flash memory performance
Reports of NAND flash device testing in the literature have for the most part been limited to examination of circuit-level parameters on raw flash chips or prototypes, and syste...
Peter Desnoyers
CORR
2010
Springer
107views Education» more  CORR 2010»
13 years 7 days ago
The E8 Lattice and Error Correction in Multi-Level Flash Memory
A construction using the E8 lattice and Reed-Solomon codes for error-correction in flash memory is given. Since E8 lattice decoding errors are bursty, a Reed-Solomon code over GF(2...
Brian M. Kurkoski
EMSOFT
2006
Springer
13 years 9 months ago
A superblock-based flash translation layer for NAND flash memory
In NAND flash-based storage systems, an intermediate software layer called a flash translation layer (FTL) is usually employed to hide the erase-before-write characteristics of NA...
Jeong-Uk Kang, Heeseung Jo, Jinsoo Kim, Joonwon Le...
TIT
2010
94views Education» more  TIT 2010»
12 years 12 months ago
Rewriting codes for joint information storage in flash memories
Abstract--Memories whose storage cells transit irreversibly between states have been common since the start of the data storage technology. In recent years, flash memories have bec...
Anxiao Jiang, Vasken Bohossian, Jehoshua Bruck
CODES
2003
IEEE
13 years 10 months ago
A low-cost memory architecture with NAND XIP for mobile embedded systems
NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and ...
Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, ...