3 search results - page 1 / 1 » Stress Aware Layout Optimization Leveraging Active Area Depe... |
TCAD
2010
12 years 11 months ago
2010
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
DATE
2008
IEEE
13 years 6 months ago
2008
IEEE
Advanced MOSFETs such as Strained Silicon (SS) devices have emerged as critical enablers to keep Moore's law on track for sub100nm technologies. Use of Strained Silicon devic...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...