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» Strong logics of first and second order
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HPCA
2005
IEEE
14 years 5 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
SODA
2010
ACM
235views Algorithms» more  SODA 2010»
14 years 2 months ago
Algorithmic Lower Bounds for Problems Parameterized by Clique-width
Many NP-hard problems can be solved efficiently when the input is restricted to graphs of bounded tree-width or clique-width. In particular, by the celebrated result of Courcelle,...
Fedor V. Fomin, Petr A. Golovach, Daniel Lokshtano...
COMPSAC
2009
IEEE
13 years 10 months ago
Tool Support for Design Pattern Recognition at Model Level
Given the rapid rise of model-driven software development methodologies, it is highly desirable that tools be developed to support the use of design patterns in this context. This...
Hong Zhu, Ian Bayley, Lijun Shan, Richard Amphlett
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
13 years 10 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
13 years 7 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang