13 search results - page 2 / 3 » Symbolic Abstraction and Deadlock-Freeness Verification of I... |
FORTE
2008
13 years 6 months ago
2008
Abstract. Several recent works have considered parameterized verification, i.e. automatic verification of systems consisting of an arbitrary number of finite-state processes organi...
ASYNC
1997
IEEE
13 years 9 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
ICST
2009
IEEE
13 years 3 months ago
2009
IEEE
Bounded model checking--as well as symbolic equivalence checking--are highly successful techniques in the hardware domain. Recently, bit-vector bounded model checkers like CBMC ha...
FDL
2007
IEEE
13 years 9 months ago
2007
IEEE
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
SPIN
2000
Springer
13 years 9 months ago
2000
Springer
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...