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» Symbolic model checking of Dual Transition Petri Nets
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ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 1 months ago
ILP Models for the Synthesis of Asynchronous Control Circuits
A new technique for the logic synthesis of asynchronous circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. The technique is ...
Josep Carmona, Jordi Cortadella
CONCUR
2000
Springer
13 years 8 months ago
Model Checking with Finite Complete Prefixes Is PSPACE-Complete
Unfoldings are a technique for verification of concurrent and distributed systems introduced by McMillan. The method constructs a finite complete prefix, which can be seen as a sym...
Keijo Heljanko
APN
2008
Springer
13 years 6 months ago
Symbolic State Space of Stopwatch Petri Nets with Discrete-Time Semantics (Theory Paper)
In this paper, we address the class of bounded Petri nets with stopwatches (SwPNs), which is an extension of T-time Petri nets (TPNs) where time is associated with transitions. Con...
Morgan Magnin, Didier Lime, Olivier H. Roux
APN
2010
Springer
13 years 9 months ago
AlPiNA: A Symbolic Model Checker
AlPiNA is a symbolic model checker for High Level Petri nets. It is comprised of two independent modules: a GUI plugin for Eclipse and an underlying model checking engine. AlPiNAâ€...
Didier Buchs, Steve Hostettler, Alexis Marechal, M...
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...